Design and biasing

Pspice simulated circuit for our design

Gain for Pspice simulation

 The design used is a single stage amplifier and this is good because it helps keep the beta value of the transistor constant and holds the base bias at a constant voltage for better stability of the circuit. The voltage entering the transistor(Vb) is derrived from the potential divider network formed by R1 and R2 in parallel and there is a voltage drop of  0.7V in order to open the transistor junctions. A different type of design involving an inductor and a capacitor in parallel at the emitter part of the transistor could have been used but that would require very tideous work as we would have to tune the LC until the output and feedback are in phase to avoid undesired noise amplification as we are dealing with high frequencies(fixed values).Also using an LC in the circuit instead will give us small bandwidth which is not ideal in this case.